Name
Abstract | ||
|---|---|---|
Bit-serial computation has been a prevailing convolution method to accelerate varying-precision DNNs by slicing a multi-bit data into multiple 1-bit data and transforming a multiplication into multiple additions, where additions of zero bits are ineffectual, while additions of non-zero bits are repetitive since multiple kernels are quite possible to possess non-zero bits at the same kernel positio... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/HPCA51647.2021.00079 | 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA) |
Keywords | DocType | ISSN |
Convolution,Neural networks,Memory management,Benchmark testing,Energy efficiency,Computational efficiency,Acceleration | Conference | 1530-0897 |
ISBN | Citations | PageRank |
978-1-6654-2235-2 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jianxun Yang | 1 | 12 | 2.80 |
| Zhao Zhang | 2 | 0 | 0.34 |
| Zhuangzhi Liu | 3 | 0 | 0.34 |
| Jing Zhou | 4 | 1 | 1.37 |
| leibo liu | 5 | 816 | 116.95 |
| Shaojun Wei | 6 | 555 | 102.32 |
| shouyi yin | 7 | 579 | 99.95 |