Name
Abstract | ||
|---|---|---|
Graphics Processing Units (GPUs) use caches to provide on-chip bandwidth as a way to address the memory wall. However, they are not always efficiently utilized for optimal GPU performance. We find that the main source of this inefficiency stems from the tightly-coupled design of cores with L1 caches. First, such a design assumes a per-core private local L1 cache in which each core independently ca... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/HPCA51647.2021.00047 | 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA) |
Keywords | DocType | ISSN |
Aggregates,Graphics processing units,Bandwidth,Organizations,Computer architecture,Traffic control,Energy efficiency | Conference | 1530-0897 |
ISBN | Citations | PageRank |
978-1-6654-2235-2 | 1 | 0.34 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohamed Assem Ibrahi | 1 | 1 | 0.34 |
| Onur Kayıran | 2 | 356 | 13.47 |
| Yasuko Eckert | 3 | 33 | 4.60 |
| Gabriel H. Loh | 4 | 12 | 1.85 |
| Adwait Jog | 5 | 568 | 23.32 |