Name
Title | ||
|---|---|---|
Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation |
Abstract | ||
|---|---|---|
High-Level Synthesis (HLS) allows to synthesize untimed behavioral descriptions into efficient RTL descriptions (Verilog or VHDL). One key advantage of HLS is that it allows to generate different micro-architectures from the same behavioral description by simply specifying different mixes of synthesis options. These include, how to synthesize arrays (e.g. RAM or registers), loops (unroll completel... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401684 | 2021 IEEE International Symposium on Circuits and Systems (ISCAS) |
Keywords | DocType | ISSN |
Measurement,VHDL,Runtime,Simulated annealing,Cost function,Space exploration,Registers | Conference | 0271-4302 |
ISBN | Citations | PageRank |
978-1-7281-9201-7 | 1 | 0.35 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yiheng Gao | 1 | 1 | 0.35 |
| Benjamin Carrión Schäfer | 2 | 78 | 25.24 |