Name
Title | ||
|---|---|---|
Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability |
Abstract | ||
|---|---|---|
ABSTRACTThis paper presents design and integration of four hardware Trojans (HTs) into a post-quantum-crypto-enhanced RISC-V micro-controller, which was taped-out in September 2020. We cover multiple HTs ranging from a simple denial-of-service HT to a side-channel HT transmitting arbitrary information to external observers. For each HT, we give estimations of the detectability by the microcontroller-integration team using design tools or by simulation. We conclude that some HTs are easily detected by design-tool warnings. Other powerful HTs, modifying software control flow, cause little disturbance, but require covert executable code modifications. With this work, we strengthen awareness for HT risks and present a realistic testing device for HT detection tools. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1145/3457388.3458869 | Computing Frontiers Conference |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexander Hepp | 1 | 0 | 0.68 |
| Georg Sigl | 2 | 447 | 62.13 |