Name
Abstract | ||
|---|---|---|
<i>Editor’s notes:</i> This article provides a theoretical baseline for enabling performance predictions across a broad spectrum of machine learning hardware architecture designs while considering the efficiency of optimizations. —<i>Sai Manoj, George Mason University</i> |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/MDAT.2021.3063340 | IEEE Design & Test |
Keywords | DocType | Volume |
Hardware,Topology,Optimization,Benchmark testing,Micromechanical devices,Task analysis,Performance evaluation | Journal | 39 |
Issue | ISSN | Citations |
3 | 2168-2356 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michaela Blott | 1 | 315 | 25.60 |
| Alina Vasilciuc | 2 | 0 | 0.34 |
| Miriam Leeser | 3 | 10 | 2.35 |
| Linda E. Doyle | 4 | 304 | 34.70 |