Name
Title | ||
|---|---|---|
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation |
Abstract | ||
|---|---|---|
This article proposes compact expressions for the jitter in clock and data recovery (CDR) circuits based on bang-bang phase detector including the phase noise of the transmitter and receiver oscillators as well as the quantization noise associated with the finite number of phases of the phase interpolator (PI) that align the receiver clock to the incoming data. Different approaches to perform the Early/Late detection on deserialized data and edge samples are compared: the use of majority voting degrades the CDR bandwidth, increasing the impact of the clock jitter on the CDR jitter; on the other hand, counting the single Early/Late occurrences does not degrade the bandwidth but increases the noise related to the finite phases of the PI. The proposed analytical formulas are validated against event-driven behavioral simulations of the CDR system including free-running oscillators as well as phase-locked loop (PLL) for clock generation. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TVLSI.2021.3068450 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
Clock and data recovery (CDR),high-speed I/O,jitter,simulation | Journal | 29 |
Issue | ISSN | Citations |
7 | 1063-8210 | 0 |
PageRank | References | Authors |
0.34 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pierpaolo Palestri | 1 | 38 | 9.24 |
| Ahmed Elnaqib | 2 | 0 | 1.01 |
| Davide Menin | 3 | 1 | 0.72 |
| Klaid Shyti | 4 | 0 | 0.34 |
| Francesco Brandonisio | 5 | 0 | 0.34 |
| A. Bandiziol | 6 | 2 | 1.45 |
| Davide Rossi | 7 | 416 | 47.47 |
| Roberto Nonis | 8 | 75 | 13.77 |