Title | ||
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Investigation Of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes From 180 Nm Bulk Cmos To 7 Nm Finfet Plus Process |
Abstract | ||
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Leakage power reduction techniques are crucial for energy-efficient circuits. This paper investigates the leakage suppression capability, performance, and reliability of dynamic leakage suppression logic (DLSL) and feedforward leakage self-suppression logic (FLSL) techniques, crossing different technology nodes from TSMC 180 nm bulk CMOS to 7 nm FinFET Plus process. Compared with CMOS benchmarks, experimental results show that DLSL-based benchmarks demonstrate a leakage power reduction for four orders of magnitude in 180 nm and 130 nm technologies, while only two orders of magnitude in other technologies. Moreover, FLSL offers a 4-28X performance improvement over DLSL at a cost of 2X leakage power. |
Year | DOI | Venue |
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2021 | 10.1109/ISCAS51556.2021.9401171 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | DocType | ISSN |
Dynamic leakage-suppression logic, feedforward leakage self-suppression logic, static power, ultra-low power, always-on low-frequency circuits | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 |
Name | Order | Citations | PageRank |
---|---|---|---|
Jieyu Li | 1 | 3 | 4.80 |
Zihan Lian | 2 | 0 | 0.34 |
Hao Zhang | 3 | 0 | 1.69 |
Weifeng He | 4 | 61 | 14.69 |
Yanan Sun | 5 | 0 | 1.69 |
Mingoo Seok | 6 | 11 | 6.77 |