Name
Abstract | ||
|---|---|---|
Implementing logic within memristive crossbar is an attractive approach to overcome the memory wall in conventional von Neumann architectures. Ternary logic with three logic levels can reduce the number of logic operations and enhance the computing speed compared to the binary logic. In this paper, a ternary logic-in-memory scheme is proposed based on the memristive dual-crossbar structure where the inputs and outputs are represented by the multi-level cells of memristors. Two inter-crossbar ternary logic gates and one intra-crossbar binary logic gate for both row and column-wise operations are supported in the proposed scheme to effectively reduce the operation latency. Experimental results show that the operation steps of the proposed multi-trit ternary adder are reduced by up to 83.82%, as compared with previously published binary memristive logic designs. The computation energy consumed by the proposed ternary adder is also reduced by up to 35.87% as compared to previously published binary IMPLY logic design. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401308 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | DocType | ISSN |
ternary logic-in-memory, memristive-crossbar, multi-level cell, ternary adder, carbon nanotube transistors | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weiyi Liu | 1 | 0 | 0.34 |
| Yanan Sun | 2 | 2 | 2.76 |
| Weifeng He | 3 | 61 | 14.69 |
| Qin Wang | 4 | 1 | 2.08 |