Name
Title | ||
|---|---|---|
A Series Stacked Finfet Structure For Digital Low Dropout Regulators With Minimum Energy Point Technique For 37.5% Energy Reduction In Cortex M0 Processor |
Abstract | ||
|---|---|---|
The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5 mu s for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5 mu s and 5mV, respectively. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401222 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | DocType | ISSN |
series stacked (SS) FinFET, dynamic voltage scaling (DVS) technique, minimum energy point (MEP) technique | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nan-Hsiung Tseng | 1 | 0 | 0.34 |
| Bo-Kuan Wu | 2 | 0 | 0.68 |
| Tzu-Ping Huang | 3 | 4 | 1.51 |
| Cheng-Yen Lee | 4 | 2 | 1.08 |
| Ke-Horng Chen | 5 | 379 | 90.04 |
| Ying-Hsi Lin | 6 | 112 | 30.84 |
| Shian-Ru Lin | 7 | 13 | 8.38 |
| Tsung-Yen Tsai | 8 | 37 | 20.41 |