Name
Abstract | ||
|---|---|---|
Resistive-RAM (ReRAM) based deep neural network (DNN) accelerator has shown great potential to address the memory wall problem for its processing-in-memory (PIM) capacity. However, ReRAM DNN accelerator still faces various challenges in its early architecture design phase due to the unpredictable variability and limitation of the ReRAM device. Software simulation helps but the simulation time is long with detailed ReRAM device model for large-scale DNNs. In this paper, we propose fast FPGA-based emulation for the DNN accelerator of ReRAM device. The emulation sets a primitive DNN accelerator architecture in FPGA and leverages FPGA hardware resources to provide massive parallelism for reducing emulation time. Meanwhile, it is co-designed with runtime software stacks to make the hardware emulation more flexible via instruction compilation and scheduling for different DNN needs. Our experiments show that the emulation can get over 194.7X speedup for large-scale DNNs against NeuroSim as a software simulator for ReRAM DNN accelerator. Therefore, the proposed emulation helps to build better ReRAM accelerators for large DNNs with much higher speed and flexibility. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401762 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | DocType | ISSN |
ReRAM, PIM, accelerator, DNN, FPGA-based emulation | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongquan Shi | 1 | 0 | 0.34 |
| Yongshuai Sun | 2 | 0 | 0.34 |
| Jianfei Jiang | 3 | 0 | 0.34 |
| Guanghui He | 4 | 0 | 3.04 |
| Qin Wang | 5 | 1 | 2.08 |
| Naifeng Jing | 6 | 152 | 27.07 |