Name
Title | ||
|---|---|---|
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation |
Abstract | ||
|---|---|---|
This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N sub-sampling phase-locked loop (SSPLL), using a low-power and low-area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401690 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | DocType | ISSN |
Calibration, digital-to-time converter (DTC), frequency synthesis, phase-locked loop (PLL), phase noise cancellation, ring oscillator, sub-sampling PLL (SSPLL), voltage-controlled delay line (VCDL) | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pratap Tumkur Renukaswamy | 1 | 2 | 1.44 |
| Nereo Markulic | 2 | 52 | 9.29 |
| Piet Wambacq | 3 | 56 | 10.11 |
| Jan Craninckx | 4 | 6 | 2.86 |