Paper Info
Title
4t Gain-Cell Providing Unlimited Availability Through Hidden Refresh With 1w1r Functionality
Abstract
Modern SoCs area and power budgets are often dominated by embedded memories on board of the chip. Gain-cell embedded DRAM is a dense, low power memory solution, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. This work presents a novel gain cell design, with robust dual read mechanism, exploiting GC-eDRAM characteristics for double write throughput, supporting low cost hidden refresh mechanism and 100% array availability, providing continuous 1W1R functionality. A 16 kbit memory macro was implemented in 65nm bulk technology offering upto 20% reduction in bitcell area compared to standard SRAM solution, and up to 3x area reduction compared to 1R1W memory solutions.
Year
DOI
Venue
2021
10.1109/ISCAS51556.2021.9401416
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Keywords
DocType
ISSN
Low Power, Gain-cell embedded DRAM (GC-eDRAM), Retention Time, Hidden Refresh, 2W2R, 1W1R, embedded Memory
Conference
0271-4302
Citations 
PageRank 
References 
0
0.34
0
Authors
5
Name
Order
Citations
PageRank
Einat Levy100.34
Aharon Sfez200.34
Roman Golman302.03
Odem Harel401.35
Adam Teman512919.12