Name
Abstract | ||
|---|---|---|
Field Programmable Gate Arrays (FPGAs) reconfigurability is a key asset for many critical applications. State-of-the-art Radiation-Hardening (Rad-Hard) methods for FPGAs consist of triplicating the logic, reinforcing the memories, and bitstream scrubbing with partial reconfiguration. These methods involve a 3x reduction of Maximal Design Capacity (MDC) and an average Time-In-Error (TIE) proportional to design sizes. In this paper, we propose an alternative: Smart-Redundancy (SR), a new method based on the detection of possible events via process and hardware modifications. Thanks to integrated particle sensors, only dual redundancy is required. Results show up to 33.33% improvement in MDC over actual Rad-Hard methods, and an average TIE decrease of at least 10,000x compared to bitstream's scrubbing, at a cost of 41.08% in area using a commercial 40nm technology node. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401092 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | DocType | ISSN |
FPGA, SEU, SET, Rad-Hard, Redundancy | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aurélien Alacchi | 1 | 1 | 2.03 |
| Edouard Giacomin | 2 | 6 | 4.23 |
| Xifan Tang | 3 | 0 | 0.34 |
| Pierre-Emmanuel Gaillardon | 4 | 355 | 55.32 |