Name
Abstract | ||
|---|---|---|
Today's microprocessors often rely on microcode updates to address issues such as security or functional patches. Unfortunately, microcode update flexibility opens up new attack vectors through malicious microcode alterations. Such attacks share many features with hardware Trojans and have similar devastating consequences for system security. However, due to microcode's opaque nature, little is known in the open literature about the capabilities and limitations of microcode Trojans. We introduce the design of a microcoded RISC-V processor architecture together with a microcode development and evaluation environment. Even though microcode typically has almost complete control of the processor hardware, the design of meaningful microcode Trojans is not straightforward. This somewhat counter-intuitive insight is due to the lack of information at the hardware level about the semantics of executed software. In three security case studies we demonstrate how to overcome these issues and give insights on how to design meaningful microcode Trojans that undermine system security. To foster future research and applications, we publicly release our implementation and evaluation platform(1). |
Year | Venue | DocType |
|---|---|---|
2021 | PROCEEDINGS OF THE 30TH USENIX SECURITY SYMPOSIUM | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nils Albartus | 1 | 1 | 4.08 |
| Clemens Nasenberg | 2 | 0 | 0.34 |
| Florian Stolz | 3 | 0 | 0.68 |
| Marc Fyrbiak | 4 | 43 | 7.18 |
| Christof Paar | 5 | 3794 | 442.62 |
| R. Tessier | 6 | 235 | 26.75 |