Name
Abstract | ||
|---|---|---|
Self-Organizing Maps (SOMs) are extensively used for data clustering and dimensionality reduction. However, if applications are to fully benefit from SOM based techniques, high-speed processing is demanding, given that data tends to be both highly dimensional and yet “big”. Hence, a fully parallel architecture for the SOM is introduced to optimize the system’s data processing time. Unlike most literature approaches, the architecture proposed here does not contain sequential steps — a common limiting factor for processing speed. The architecture was validated on FPGA and evaluated concerning hardware throughput and the use of resources. Comparisons to the state of the art show a speedup of 8.91× over a partially serial implementation, using less than 15% of hardware resources available. Thus, the method proposed here points to a hardware architecture that will not be obsolete quickly. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1016/j.neunet.2021.05.021 | Neural Networks |
Keywords | DocType | Volume |
Self-Organizing Map,Parallel design,Hardware,FPGA | Journal | 143 |
Issue | ISSN | Citations |
1 | 0893-6080 | 0 |
PageRank | References | Authors |
0.34 | 9 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Leonardo A Dias | 1 | 0 | 1.01 |
| Augusto M P Damasceno | 2 | 0 | 0.34 |
| Elena I. Gaura | 3 | 60 | 14.53 |
| M. A.C. Fernandes | 4 | 15 | 8.23 |