Name
Title | ||
|---|---|---|
Application-driven design exploration for dense ferroelectric embedded non-volatile memories |
Abstract | ||
|---|---|---|
ABSTRACTThe memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device characteristics, programming schemes, and memory array architecture, and explore different design choices to optimize performance, energy, area, and accuracy metrics for critical data-intensive workloads. From our cross-stack design exploration, we find that we can store DNN weights and social network graphs at a density of over 8MB/mm2 and sub-2ns read access latency without loss in application accuracy. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISLPED52811.2021.9502489 | ISLPED |
Keywords | DocType | ISSN |
application-driven design exploration,dense ferroelectric embedded nonvolatile memories,memory wall bottleneck,data-intensive applications,multilevel FeFET-based,reliable multilevel cell storage,design overhead costs,energy-efficient on-chip memory,application accuracy,cross-stack design exploration,critical data-intensive workloads,memory array architecture,FeFET device characteristics,time 2.0 ns | Conference | 1533-4678 |
ISBN | Citations | PageRank |
978-1-6654-3923-7 | 1 | 0.37 |
References | Authors | |
0 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad Mehdi Sharifi | 1 | 4 | 2.48 |
| Lillian Pentecost | 2 | 19 | 4.41 |
| Ramin Rajaei | 3 | 1 | 2.06 |
| Arman Kazemi | 4 | 1 | 2.06 |
| Qiuwen Lou | 5 | 22 | 5.23 |
| Gu-Yeon Wei | 6 | 2 | 1.40 |
| David Brooks | 7 | 5518 | 422.08 |
| Kai Ni | 8 | 6 | 2.93 |
| X. Sharon Hu | 9 | 7 | 1.57 |
| Michael Niemier | 10 | 191 | 31.85 |
| Marco Donato | 11 | 31 | 5.83 |