Name
Abstract | ||
|---|---|---|
Adiabatic logic families employing four phase trapezoidal power clock, require T/4 phase shift between the input and clock and therefore require insertion of additional buffer for synchronization. This manuscript proposes Clock Aligned Input Adiabatic Logic (CAIAL) which eliminates the T/4 phase shift requirement between the clock and inputs, having similar power requirements as existing adiabatic logic families. The proposed design (CAIAL) dissipates lesser power as compared to its CMOS and FinFET counterparts. Ripple Carry Adder (RCA) and Kogge Stone Adder (KSA) of varying bit widths using existing and proposed methodologies have been designed. The functionality of all the circuits is verified using 32 nm PTM HP technology parameters in Tanner T-Spice™. A significant reduction in buffer count and power saving of 35% in RCA and 22% in KSA is achieved across all bit widths at 500 MHz. The robustness of the proposed 2N2N2P-CAIAL combination to process, voltage and clock skew variations have also been proven. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1016/j.mejo.2021.105122 | Microelectronics Journal |
Keywords | DocType | Volume |
Adiabatic logic,Buffer reduction,Clock aligned input adiabatic logic,CAIAL,Low power design | Journal | 114 |
ISSN | Citations | PageRank |
0026-2692 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aditya S. Kumar | 1 | 0 | 0.34 |
| Sagar Jain | 2 | 123 | 5.63 |
| Neeta Pandey | 3 | 0 | 0.34 |