Name
Title | ||
|---|---|---|
Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal |
Abstract | ||
|---|---|---|
Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR f... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCSII.2021.3081257 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Finite impulse response filters,Computer architecture,Hardware,Cascading style sheets,Signal processing algorithms,Filtering algorithms,Band-pass filters | Journal | 68 |
Issue | ISSN | Citations |
11 | 1549-7747 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sudipta Bose | 1 | 0 | 0.34 |
| Arijit De | 2 | 3 | 4.25 |
| Indrajit Chakrabarti | 3 | 65 | 19.85 |