Name
Abstract | ||
|---|---|---|
This paper presents a statistical offset calibration technique for 1.5-bit/cycle successive approximation register (SAR) analog-to-digital converters (ADCs). It estimates the offset polarity by comparing the number of 0 and 1 in specific conversion cycles and performs compensation in the analog domain. Compared to prior works based on zero input injection, the proposed method avoids the metastability issue which influences the calibration accuracy and convergence. As a proof of concept, an 8-bit 350-MS/s SAR ADC with 1.5-bit/cycle operation and offset calibration is fabricated in 65-nm CMOS. Measurement results show that after offset calibration, the SNDR and SFDR are improved by 5.6 dB and 5.9 dB, respectively. The active area of the calibration circuit is 0.01 mm2. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1016/j.mejo.2021.105114 | Microelectronics Journal |
Keywords | DocType | Volume |
ADC,SAR,Comparator offset,1.5-bit/cycle,Offset calibration | Journal | 114 |
ISSN | Citations | PageRank |
0026-2692 | 0 | 0.34 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dengquan Li | 1 | 0 | 0.68 |
| Maliang Liu | 2 | 0 | 0.68 |
| Shubin Liu | 3 | 0 | 0.34 |
| Yuhua Liang | 4 | 0 | 0.68 |
| Ruixue Ding | 5 | 0 | 0.34 |