Name
Title | ||
|---|---|---|
Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure |
Abstract | ||
|---|---|---|
This brief presents a novel pipelined VLSI architecture for computing discrete wavelet packet transform (DWPT) with an arbitrary wavelet tree. Coefficients for different levels are computed in a series of stages. Each stage consists of a bypassed wavelet filter and circuit for reordering intermediate coefficients. The proposed lifting-based wavelet filter computes high- and low-pass coefficients in series. In order to accommodate the arbitrary tree structure, the filter either computes the coefficients or bypass the samples. The reordering of intermediate coefficients forms a subband required for next-level computation. The coefficients are computed in a serial manner and reordering of intermediate coefficients reduce not only the memory elements but also the circuit complexity. The proposed pipelined architecture reduces the requirement of memory elements by 50%. Furthermore, the hardware implementation results show that the area and power requirement are reduced by 33% and 20%, respectively. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TVLSI.2021.3079989 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
Arbitrary tree structure,bit-reordering,discrete wavelet packet transform (DWPT),signal flow graph (SFG) | Journal | 29 |
Issue | ISSN | Citations |
7 | 1063-8210 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gyanendra Singh | 1 | 0 | 0.34 |
| Samba Raju Chiluveru | 2 | 1 | 1.70 |
| Balasubramanian Raman | 3 | 679 | 70.23 |
| Manoj Tripathy | 4 | 0 | 0.34 |
| Brajesh Kumar Kaushik | 5 | 56 | 21.31 |