Name
Title | ||
|---|---|---|
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture |
Abstract | ||
|---|---|---|
Coarse-Grained Reconfigurable Arrays (CGRAs) are promising to have low power consumption and high energy-efficiency characteristics as accelerators. Recent years, many research works focus on improving the programmability of the CGRAs by enabling the fast reconfiguration during execution. The performance of these CGRAs critically hinges upon the scheduling power of the compiler. One of the critica... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.23919/DATE51398.2021.9473971 | 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Keywords | DocType | ISBN |
Power demand,Heuristic algorithms,Software algorithms,Bandwidth,Software,Scheduling,System-on-chip | Conference | 978-3-9819263-5-4 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuge Chen | 1 | 0 | 0.34 |
| Zhongyuan Zhao | 2 | 9 | 5.24 |
| Jianfei Jiang | 3 | 0 | 0.68 |
| Guanghui He | 4 | 0 | 3.04 |
| Zhigang Mao | 5 | 199 | 41.73 |
| Weiguang Sheng | 6 | 33 | 8.08 |