Name
Title | ||
|---|---|---|
Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs |
Abstract | ||
|---|---|---|
This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ~ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/OJCAS.2020.2994838 | IEEE Open Journal of Circuits and Systems |
Keywords | DocType | Volume |
Tri-level,current-steering,DACs,thermal noise,DNL,INL,HD3,SFDR | Journal | 1 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shantanu Mehta | 1 | 0 | 1.69 |
| Daniel O'Hare | 2 | 0 | 0.68 |
| Vincent O'Brien | 3 | 0 | 1.69 |
| Eric Thompson | 4 | 0 | 1.01 |
| Brendan Mullane | 5 | 3 | 1.44 |