Name
Title | ||
|---|---|---|
A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm<sup>2</sup> Switched-Capacitor DAC in 16-nm FinFET CMOS |
Abstract | ||
|---|---|---|
This article presents a compact 2× time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC's architecture is based on parallel charge redistribution and separates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
in 16-nm CMOS and supports up to 0.32- V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub>
signal swing across its differential 100- Ω load. It achieves an SFDR ≥ 37 dB and an IM 3 ≤ -45.6 dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/JSSC.2021.3057608 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Digital-to-analog converter (DAC),switched-capacitor (SC) circuits,time interleaving | Journal | 56 |
Issue | ISSN | Citations |
8 | 0018-9200 | 2 |
PageRank | References | Authors |
0.45 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pietro Caragiulo | 1 | 2 | 1.13 |
| Oscar Elisio Mattia | 2 | 2 | 0.79 |
| Amin Arbabian | 3 | 2 | 1.13 |
| Boris Murmann | 4 | 594 | 82.64 |