Title | ||
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A5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers |
Abstract | ||
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We present a CMOS imager for low-latency face detection empowered by parallel imaging and computing of machine-learning (ML) classifiers. The energy-efficient parallel operation and multi-scale detection eliminate image capture delay and significantly alleviate backend computational loads. The proposed pixel architecture, composed of dynamic samplers in a global shutter (GS) pixel array, allows for energy-efficient in-memory charge-domain computing of feature extraction and classification. The illumination-invariant detection was realized by using log-Haar features. A prototype 240×240 imager achieved an on-chip face detection latency of 5.1ms with a 97.9% true positive rate and 2% false positive rate at 120fps. Moreover, a dynamic nature of in-memory computing allows an energy efficiency of 419pJ/pixel for feature extraction and classification, leading to the smallest latency-energy product of 3.66ms∙nJ/pixel with digital backend processing. |
Year | DOI | Venue |
---|---|---|
2021 | 10.23919/VLSICircuits52068.2021.9492432 | 2021 Symposium on VLSI Technology |
DocType | ISSN | ISBN |
Conference | 0743-1562 | 978-1-6654-3009-8 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Hyunsoo Song | 1 | 0 | 0.34 |
Sungjin Oh | 2 | 0 | 0.34 |
Juan Salinas | 3 | 0 | 0.34 |
Sung-Yun Park | 4 | 0 | 0.34 |
Euisik Yoon | 5 | 109 | 16.58 |