Name
Title | ||
|---|---|---|
A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.23919/VLSICircuits52068.2021.9492420 | VLSI Circuits |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yang Wang | 1 | 394 | 61.44 |
| Yubin Qin | 2 | 1 | 2.04 |
| Dazheng Deng | 3 | 0 | 1.69 |
| Jingchuan Wei | 4 | 0 | 0.34 |
| Tianbao Chen | 5 | 0 | 0.34 |
| Xinhan Lin | 6 | 11 | 2.62 |
| Leibo Liu | 7 | 2 | 1.39 |
| Shaojun Wei | 8 | 2 | 1.39 |
| Shouyi Yin | 9 | 1 | 1.71 |