Title
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference
Abstract
We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.
Year
DOI
Venue
2021
10.23919/VLSICircuits52068.2021.9492403
2021 Symposium on VLSI Technology
Keywords
DocType
ISSN
In-memory computing,custom ISA,DNN accelerator
Conference
0743-1562
ISBN
Citations 
PageRank 
978-1-6654-3009-8
0
0.34
References 
Authors
0
10
Name
Order
Citations
PageRank
Shihui Yin17110.03
Bo Zhang200.68
Minkyu Kim3229.55
Jyotishman Saikia400.68
Soonwan Kwon500.68
Sungmeen Myung600.68
Hyunsoo Kim700.68
Sang Joon Kim800.68
Mingoo Seok900.34
Jae-sun Seo1053656.32