Title | ||
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PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference |
Abstract | ||
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We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply. |
Year | DOI | Venue |
---|---|---|
2021 | 10.23919/VLSICircuits52068.2021.9492403 | 2021 Symposium on VLSI Technology |
Keywords | DocType | ISSN |
In-memory computing,custom ISA,DNN accelerator | Conference | 0743-1562 |
ISBN | Citations | PageRank |
978-1-6654-3009-8 | 0 | 0.34 |
References | Authors | |
0 | 10 |
Name | Order | Citations | PageRank |
---|---|---|---|
Shihui Yin | 1 | 71 | 10.03 |
Bo Zhang | 2 | 0 | 0.68 |
Minkyu Kim | 3 | 22 | 9.55 |
Jyotishman Saikia | 4 | 0 | 0.68 |
Soonwan Kwon | 5 | 0 | 0.68 |
Sungmeen Myung | 6 | 0 | 0.68 |
Hyunsoo Kim | 7 | 0 | 0.68 |
Sang Joon Kim | 8 | 0 | 0.68 |
Mingoo Seok | 9 | 0 | 0.34 |
Jae-sun Seo | 10 | 536 | 56.32 |