Name
Abstract | ||
|---|---|---|
ABSTRACTConventional electronic memory hierarchies are intrinsically limited in their ability to overcome the memory wall due to scaling constraints. Optical caches and interconnects can mitigate these constraints, and enable processors to reach performance and energy efficiency unattainable by purely electronic means. However, the promised benefits cannot be realized through a simple replacement process; to reach its full potential, the architecture needs to be holistically redesigned. This paper proposes Pho$, an opto-electronic memory hierarchy architecture for multicores. Pho$ replaces conventional core-private electronic caches with a large shared optical L1 built with optical SRAMs. A novel optical NoC provides low-latency and high-bandwidth communication between the electronic cores and the shared optical L1 at low optical loss. Our results show that Pho$ achieves on average 1.41x performance speedup (3.89x max) and 31% lower energy-delay product (90% max) against conventional designs. Moreover, the optical NoC for core-cache communication consumes 70% less power compared to directly applying previously-proposed optical NoC architectures. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISLPED52811.2021.9502487 | ISLPED |
Keywords | DocType | ISSN |
shared optical cache hierarchies,memory wall,scaling constraints,energy efficiency,opto-electronic memory hierarchy architecture,optical SRAMs,novel optical NoC,electronic cores,low optical loss | Conference | 1533-4678 |
ISBN | Citations | PageRank |
978-1-6654-3923-7 | 0 | 0.34 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haiyang Han | 1 | 0 | 0.34 |
| t alexoudi | 2 | 1 | 4.42 |
| christos vagionas | 3 | 6 | 7.31 |
| Nikos Pleros | 4 | 25 | 23.69 |
| Nikos Hardavellas | 5 | 1015 | 44.39 |