Name
Abstract | ||
|---|---|---|
In this paper, a scalable and passive component-less power-clock generation for adiabatic logic circuits, inclusive of the adiabatic core, is presented. The power-clock is traditionally a sinusoidal signal, that acts as the power and timing source to adiabatic gates. The slope of the power-clock signal directly impacts the overall energy efficiency of the adiabatic gates. Prior works have consider... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISVLSI51109.2021.00068 | 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | DocType | ISSN |
Technological innovation,RLC circuits,Adiabatic,Logic gates,Very large scale integration,Throughput,Energy efficiency | Conference | 2159-3469 |
ISBN | Citations | PageRank |
978-1-6654-3946-6 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ragh Kuttappa | 1 | 0 | 2.37 |
| Leo Filippini | 2 | 6 | 2.91 |
| Nicholas Sica | 3 | 0 | 0.34 |
| Baris Taskin | 4 | 1 | 1.03 |