Name
Title | ||
|---|---|---|
A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs |
Abstract | ||
|---|---|---|
The long latency feature of the conventional lookup tables (LUTs) puts a limit on their applications in a VCO-based continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC). In this paper, a latency-optimized scheme is proposed to break this limitation. The search process of the LUT is achieved by a multi-step procedure to calculate the number of '1' in the address code with low latency. The LUT is designed in a 180-nm CMOS process. Compared to a conventional implementation, the latency can be reduced by 25% with the proposed technique. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/MWSCAS47672.2021.9531839 | 2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) |
Keywords | DocType | ISSN |
LUT, nonlinearity calibration, VCO-based CTSD | Conference | 1548-3746 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yanlin He | 1 | 0 | 0.34 |
| Yuekang Guo | 2 | 2 | 3.40 |
| Jing Jin | 3 | 3 | 5.49 |
| JianJun Zhou | 4 | 0 | 5.07 |