Name
Abstract | ||
|---|---|---|
Due to its speed in cross-executing sequential code, dynamic binary translation is the unchallenged technology for full system-level simulation. Among the translators, QEMU has become the de facto solution. It introduced parallel host execution of the target cores a few years ago for the ARM instruction set architecture and this support is now also available, among others, for RISC-V. Given the po... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/DSD53832.2021.00045 | 2021 24th Euromicro Conference on Digital System Design (DSD) |
Keywords | DocType | ISBN |
Reduced instruction set computing,Scalability,Linux,Switched mode power supplies,Benchmark testing,Parallel processing,Time measurement | Conference | 978-1-6654-2703-6 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marie Badaroux | 1 | 0 | 0.34 |
| Saverio Miroddi | 2 | 0 | 0.34 |
| Frédéric Pétrot | 3 | 0 | 0.34 |