Name
Abstract | ||
|---|---|---|
Clock Skew Scheduling has become a common practice in state-of-the-art FPGAs with the introduction of delay chains on the clock path in the hardware of both Xilinx and Intel® FPGAs, as well as clock skew scheduling algorithms in the CAD tools. Ideally, globally optimal solutions are sought to find the best solution across the entire design. However, using Mixed-Integer Linear Programmin... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/FPL53798.2021.00064 | 2021 31st International Conference on Field-Programmable Logic and Applications (FPL) |
Keywords | DocType | ISSN |
Runtime,Costs,Scheduling algorithms,Tools,Performance gain,Scheduling,Hardware | Conference | 1946-1488 |
ISBN | Citations | PageRank |
978-1-6654-3759-2 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Grace Zgheib | 1 | 21 | 6.40 |
| Yu Shen Lu | 2 | 0 | 0.34 |
| Ilya Ganusov | 3 | 0 | 0.68 |