Name
Title | ||
|---|---|---|
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS |
Abstract | ||
|---|---|---|
High-level synthesis (HLS) automatically transforms high-level programs in a language such as C/C++ into a low-level hardware description. In this context, loop pipelining is a key optimisation method for improving hardware performance. The main performance bottleneck of a pipelined loop is the ratio between two values: the latency of each iteration and the dependence distance of the operations in... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/FPL53798.2021.00066 | 2021 31st International Conference on Field-Programmable Logic and Applications (FPL) |
Keywords | DocType | ISSN |
High-Level Synthesis,Loop Pipelining,Formal Methods | Conference | 1946-1488 |
ISBN | Citations | PageRank |
978-1-6654-3759-2 | 1 | 0.38 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jianyi Cheng | 1 | 3 | 2.44 |
| John Wickerson | 2 | 142 | 10.08 |
| George A. Constantinides | 3 | 1391 | 160.26 |