Name
Abstract | ||
|---|---|---|
This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3rd-order Cascade of Integrator with Feed Forward (CIFF) with a 4-bit quantizer, and it achieves a peak SNDR of 67dB and DR of 70.0dB with 47.5MHz bandwidth when clocked at 950MHz. This is the highest bandwidth rep... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ESSCIRC53450.2021.9567814 | ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) |
Keywords | DocType | ISSN |
Multi-stage noise shaping,Sigma-delta modulation,Power demand,Europe,Peak to average power ratio,Delta-sigma modulation,Solid state circuits | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-6654-3751-6 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lucas Moura Santana | 1 | 0 | 0.68 |
| Ewout Martens | 2 | 75 | 17.77 |
| Jorge Lagos | 3 | 18 | 5.57 |
| Benjamin P. Hershberg | 4 | 180 | 23.21 |
| Piet Wambacq | 5 | 529 | 96.10 |
| Jan Craninckx | 6 | 6 | 2.86 |