Name
Title | ||
|---|---|---|
A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC |
Abstract | ||
|---|---|---|
This paper presents a high-bandwidth, high-resolution continuous-time incremental ΣΔ-modulator employing a 6-tap finite impulse response (FIR) feedback digital-to-analog converter (DAC) for improved clock jitter immunity. Resetting the FIR filter internal states in the incremental mode introduces initial transient overshoots, which can cause instability at high input amplitudes. To solve this prob... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ESSCIRC53450.2021.9567762 | ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) |
Keywords | DocType | ISSN |
Sigma-delta modulation,Power demand,Frequency modulation,Finite impulse response filters,Linearity,Prototypes,Interference | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-6654-3751-6 | 2 | 0.49 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayman Sakr | 1 | 2 | 1.51 |
| Mohamed Atef Hassan | 2 | 2 | 1.51 |
| Jens Anders | 3 | 60 | 24.75 |