Paper Info
Title
Digital PLLs: the modern timing reference for radar and communication systems
Abstract
Digital PLLs are nowadays recognized as a viable approach for the design of high-performance frequency synthesizers in scaled CMOS technologies. Latest implementations allow achieving at low power both state-of-the-art rms jitter, between 50fs and 100fs, and highly linear fast frequency modulation capability, thus enabling both high-efficiency communications systems and radar applications in CMOS....
Year
DOI
Venue
2021
10.1109/ESSCIRC53450.2021.9567810
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Keywords
DocType
ISSN
Frequency synthesizers,Frequency modulation,Communication systems,Jitter,Calibration,Topology,Timing
Conference
1930-8833
ISBN
Citations 
PageRank 
978-1-6654-3751-6
2
0.36
References 
Authors
0
2
Name
Order
Citations
PageRank
Carlo Samori121.04
Luca Bertulessi2154.73