Name
Abstract | ||
|---|---|---|
ABSTRACTWe present Xenon, a solver-aided, interactive method for formally verifying that Verilog hardware executes in constant-time. Xenon scales to realistic hardware designs by drastically reducing the effort needed to localize the root cause of verification failures via a new notion of constant-time counterexamples, which Xenon uses to synthesize a minimal set of secrecy assumptions in an interactive verification loop. To reduce verification time Xenon exploits modularity in Verilog code via module summaries, thereby avoiding duplicate work across multiple module instantiations. We show how Xenon's assumption synthesis and summaries enable us to verify different kinds of circuits, including a highly modular AES- 256 implementation where modularity cuts verification from six hours to under three seconds, and the ScarVside-channel hardened RISC-V micro-controller whose size exceeds previously verified designs by an order of magnitude. In a small study, we also find that Xenon helps non-expert users complete verification tasks correctly and faster than previous state-of-art tools. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1145/3460120.3484810 | Computer and Communications Security |
Keywords | DocType | Citations |
constant-time, side-channels, hardware, verification | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Klaus von Gleissenthall | 1 | 21 | 3.47 |
| Rami Gökhan Kıcı | 2 | 5 | 1.75 |
| Deian Stefan | 3 | 418 | 29.21 |
| Ranjit Jhala | 4 | 2183 | 111.68 |