Name
Title | ||
|---|---|---|
Analysis Of Current Aggregation In Gate-Control Dual Direction Silicon Controlled Rectifier |
Abstract | ||
|---|---|---|
The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (V-h). Two GC-DDSCRs are fabricated in a 0.5 mu m CMOS technology and tested by transmission line pulse (TLP). The V-h increases from 13.84V to 16.44V as the gate size expands from 2.5 mu m to 4.5 mu m. The mechanism of current aggregation is verified. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1587/elex.18.20210214 | IEICE ELECTRONICS EXPRESS |
Keywords | DocType | Volume |
silicon controlled rectifier, electroStatic discharge, CMOS technology | Journal | 18 |
Issue | ISSN | Citations |
13 | 1349-2543 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zeyu Zhong | 1 | 0 | 0.34 |
| Yang Wang | 2 | 0 | 0.68 |
| Xiangliang Jin | 3 | 0 | 1.35 |
| Yan Peng | 4 | 2 | 2.39 |
| Jun Luo | 5 | 0 | 0.34 |
| Jun Yang | 6 | 0 | 0.34 |