Name
Title | ||
|---|---|---|
The Fractional-N All Digital Frequency Locked Loop With Robustness For Pvt Variation And Its Application For The Microcontroller Unit |
Abstract | ||
|---|---|---|
This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 mu m CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1587/transinf.2020LOP0008 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | DocType | Volume |
all digital frequency locked loop, fractional-N, PVT variation, microcontroller unit | Journal | E104D |
Issue | ISSN | Citations |
8 | 1745-1361 | 0 |
PageRank | References | Authors |
0.34 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ryoichi Miyauchi | 1 | 0 | 0.34 |
| Akio Yoshida | 2 | 0 | 0.34 |
| Shuya Nakano | 3 | 0 | 0.34 |
| Hiroki Tamura | 4 | 72 | 21.29 |
| Koichi Tanno | 5 | 0 | 0.34 |
| Yutaka Fukuchi | 6 | 0 | 0.34 |
| Yukio Kawamura | 7 | 0 | 0.34 |
| Yuki Kodama | 8 | 0 | 0.34 |
| Yuichi Sekiya | 9 | 0 | 0.34 |