Title
Sparse Matrix-Vector Multiplication Cache Performance Evaluation and Design Exploration
Abstract
In this paper, we conducted a group of evaluations on the SpMV kernel with sequential implementation to investigate cache performance on single-core platforms. We verified a similar pattern inside a suite of sparse matrices covering various domains, which makes cache hit rate extraordinary inspiring in a sequential environment. This implicit regularity drove us to propose a cache space splitting a...
Year
DOI
Venue
2021
10.1109/MASCOTS53633.2021.9614301
2021 29th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)
Keywords
DocType
ISBN
Performance evaluation,Analytical models,Program processors,Computational modeling,Space exploration,Telecommunications,Pins
Conference
978-1-6654-5838-2
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Jianfeng Cui100.34
Kai Lu200.34
Sheng Liu374.06