Name
Title | ||
|---|---|---|
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits |
Abstract | ||
|---|---|---|
Timing error detection is a key technique for resilient circuits to explore the timing margins, yet it hinders the scan shift operations and increases the excessive test overhead. In this paper, we propose an area-efficient scannable in situ timing error detection technique consisting of a lightweight scannable error-detection cell and propagation logics, featuring low design-for-test effort and t... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ICCAD51958.2021.9643525 | 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) |
Keywords | DocType | ISSN |
Protocols,Latches,Design automation,Benchmark testing,Design for testability,Delays,Logic testing | Conference | 1933-7760 |
ISBN | Citations | PageRank |
978-1-6654-4507-8 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao Zhang | 1 | 0 | 1.69 |
| Weifeng He | 2 | 61 | 14.69 |
| Yanan Sun | 3 | 2 | 2.76 |
| Mingoo Seok | 4 | 11 | 6.77 |