Title
Multilevel simulation-based co-design of next generation HPC microprocessors
Abstract
This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation speed, accuracy and model abstraction level, and are shown to be complementary. We apply the MUSA trace-based simulator for the initial sizing of vector register length, system-le...
Year
DOI
Venue
2021
10.1109/PMBS54543.2021.00008
2021 International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS)
Keywords
DocType
ISBN
Co-design,Simulation,Emulation,Benchmarking,HPC
Conference
978-1-6654-1118-9
Citations 
PageRank 
References 
1
0.37
0
Authors
20