Name
Abstract | ||
|---|---|---|
In this brief, a high-throughput Huffman encoder VLSI architecture based on the Canonical Huffman method is proposed to improve the encoding throughput and decrease the encoding time required by the Huffman code word table construction process. We proposed parallel computing architectures for frequency-statistical sorting and code-size computational sorting. This architecture results in a process ... |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/TCSII.2021.3091611 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Computer architecture,Sorting,Image coding,Microprocessors,Encoding,Very large scale integration,Clocks | Journal | 69 |
Issue | ISSN | Citations |
1 | 1549-7747 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhenyu Shao | 1 | 0 | 0.34 |
| Zhixiong Di | 2 | 2 | 3.09 |
| Quanyuan Feng | 3 | 147 | 25.34 |
| Qiang Wu | 4 | 0 | 0.68 |
| Yibo Fan | 5 | 8 | 7.71 |
| Xulin Yu | 6 | 0 | 0.34 |
| Wenqiang Wang | 7 | 0 | 0.34 |