Name
Abstract | ||
|---|---|---|
Flip-flops are a key component of digital integrated circuits and substantially affect their power and energy consumption. In this paper, an ultra low-power, contention-free, static single-phase 3-transistors clock load flip-flop is described and referred to as 19-T Ultra Low-power Flip-flop (ULFF). Simulation results in CMOS 65 nm technology show that at nominal conditions and Data Activity (DA) ... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ICECS53924.2021.9665485 | 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) |
Keywords | DocType | ISBN |
Energy consumption,Simulation,Conferences,Digital integrated circuits,Voltage,CMOS technology,Energy efficiency | Conference | 978-1-7281-8281-0 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yugal Maheshwari | 1 | 0 | 0.34 |
| Kleber Stangherlin | 2 | 0 | 0.34 |
| Derek Wright | 3 | 0 | 0.34 |
| Manoj Sachdev | 4 | 1 | 0.71 |