Title
Evaluation of Stacked-CNTFET Structures for High-performance Applications
Abstract
The performance trade-off for FET structures with different arrangements of vertically stacked CNTs, including single columns and matrices, is investigated by 3D device simulation including known relevant physical effects such as carrier tunneling through the contact barriers, scattering transport in the channel and electrostatic screening effects. While a single tube gate-all-around (GAA) based s...
Year
DOI
Venue
2021
10.1109/BCICTS50416.2021.9682469
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)
Keywords
DocType
ISBN
Performance evaluation,Solid modeling,Three-dimensional displays,Metallization,Gallium arsenide,Logic gates,Tunneling
Conference
978-1-6654-3990-9
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
Boli Peng100.34
Sven Mothes200.34
Manojkumar Annamalai300.34
Michael Schröter400.34