Paper Info
Title
Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs
Abstract
This article presents a reconfigurable accelerator for REcurrent Neural networks with fine-grained cOlumn-Wise matrix–vector multiplicatioN (RENOWN). We propose a novel latency-hiding architecture for recurrent neural network (RNN) acceleration using column-wise matrix–vector multiplication (MVM) instead of the state-of-the-art row-wise operation. This hardware (HW) architecture can eliminate data dependencies to improve the throughput of RNN inference systems. Besides, we introduce a configurable checkerboard tiling strategy which allows large weight matrices, while incorporating various configurations of element-based parallelism (EP) and vector-based parallelism (VP). These optimizations improve the exploitation of parallelism to increase HW utilization and enhance system throughput. Evaluation results show that our design can achieve over 29.6 tera operations per second (TOPS) which would be among the highest for field-programmable gate array (FPGA)-based RNN designs. Compared to state-of-the-art accelerators on FPGAs, our design achieves 3.7–14.8 times better performance and has the highest HW utilization.
Year
DOI
Venue
2022
10.1109/TVLSI.2021.3135353
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
DocType
Volume
Hardware Accelerator,long short-term (LSTM),recurrent neural network (RNN)
Journal
30
Issue
ISSN
Citations 
2
1063-8210
0
PageRank 
References 
Authors
0.34
0
10
Name
Order
Citations
PageRank
Zhiqiang Que100.34
Hiroki Nakahara200.34
Eriko Nurvitadhi339933.08
Andrew Boutros400.34
Hongxiang Fan5237.57
Chenglong Zeng671.88
Jiuxi Meng752.14
Kuen Hung Tsoi801.69
Xinyu Niu900.34
Wayne Luk1000.34