Name
Abstract | ||
|---|---|---|
A low power and high-speed sample-and-hold (S/H) circuit which is suitable for the 16bit pipelined analog-to-digital converter (ADC) is proposed. By using the dynamic bias technique, The OTA in the S/H is realized with lower power dissipation. This S/H is fabricated in
<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18\ \mu\ \mathrm{m}$</tex>
mixed signal CMOS process and occupies 0.128mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
. It is integrated in a 16bit 25MS/s pipelined ADC which delivers up to 96.2dB spur-free dynamic range (SFDR) and 75.5dB signal to noise and distortion ratio (SINAD) with 30.1MHz input tone, while the power dissipation is only 34.7mW. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/APCCAS51387.2021.9687731 | 2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS) |
Keywords | DocType | ISBN |
OTA,GBW,pipelined,ADC,CMOS | Conference | 978-1-6654-3917-6 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaodan Zhou | 1 | 0 | 0.34 |
| Zehao Li | 2 | 0 | 0.34 |
| Yujie Wang | 3 | 0 | 0.34 |
| Xiong Zhou | 4 | 1 | 0.70 |
| Shiheng Yang | 5 | 1 | 0.70 |
| Jiaxin Liu | 6 | 0 | 0.34 |
| qiang li | 7 | 8 | 7.55 |