Title | ||
---|---|---|
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC |
Abstract | ||
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This paper presents a tri-gear ARMv9 CPU subsystem incorporated in a 5G flagship mobile SoC. Implemented in a 5nm technology node, a 3.4GHz High-Performance (HP) core is introduced along with circuit and implementation techniques to achieve CPU PPA targets. A die photograph is shown in Fig. 2.5.7. The SoC integrates a 5G modem supporting NR sub-6GHz with downlink and uplink speed up to 7.01Gb/s an... |
Year | DOI | Venue |
---|---|---|
2022 | 10.1109/ISSCC42614.2022.9731604 | 2022 IEEE International Solid- State Circuits Conference (ISSCC) |
Keywords | DocType | Volume |
Image resolution,Three-dimensional displays,5G mobile communication,Graphics processing units,Streaming media,Modems,Central Processing Unit | Conference | 65 |
ISBN | Citations | PageRank |
978-1-6654-2800-2 | 0 | 0.34 |
References | Authors | |
0 | 26 |
Name | Order | Citations | PageRank |
---|---|---|---|
Ashish Nayak | 1 | 0 | 0.34 |
HsinChen Chen | 2 | 0 | 0.34 |
Hugh Mair | 3 | 0 | 0.34 |
Rolf Lagerquist | 4 | 0 | 0.34 |
Tao Chen | 5 | 0 | 0.34 |
Anand Rajagopalan | 6 | 0 | 0.34 |
Gordon Gammie | 7 | 0 | 0.34 |
Ramu Madhavaram | 8 | 0 | 0.34 |
Madhur Jagota | 9 | 0 | 0.34 |
CJ Chung | 10 | 0 | 0.34 |
Jenny Wiedemeier | 11 | 0 | 0.34 |
Bala Meera | 12 | 0 | 0.34 |
Chao-Yang Yeh | 13 | 0 | 0.34 |
Maverick Lin | 14 | 0 | 0.34 |
Curtis Lin | 15 | 0 | 0.34 |
Vincent Lin | 16 | 0 | 0.34 |
Jiun Lin | 17 | 0 | 0.34 |
YS Chen | 18 | 0 | 0.34 |
Barry Chen | 19 | 0 | 0.34 |
Cheng-Yuh Wu | 20 | 0 | 0.34 |
Ryan ChangChien | 21 | 0 | 0.34 |
Ray Tzeng | 22 | 0 | 0.34 |
Kelvin Yang | 23 | 0 | 0.34 |
Achuta Thippana | 24 | 0 | 0.34 |
Ericbill Wang | 25 | 0 | 0.34 |
SA Hwang | 26 | 0 | 0.34 |