Paper Info
Title
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse
Abstract
Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.23\times / 3.06\times $ </tex-math></inline-formula> higher compared with the state-of-the-art CIM macros and processors.
Year
DOI
Venue
2022
10.1109/JSSC.2022.3148273
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Adaptive power-OFF,block-wise sparsity (BWS),computing-in-memory (CIM),data-reuse architecture,neural network (NN) processor
Journal
57
Issue
ISSN
Citations 
8
0018-9200
0
PageRank 
References 
Authors
0.34
26
10
Name
Order
Citations
PageRank
J Yue111.05
Y. J. Liu21116.87
Z Yuan322.43
X Feng410.71
Y He501.01
Weidong Sun610416.84
X. Z. Zhang71113.15
Xiao-Sheng Si862346.17
G. R. Liu92310.39
James Z. Wang107526403.00