Paper Info
Title
WDBT: Non-volatile memory wear characterization and mitigation for DBT systems
Abstract
Emerging high-capacity and byte-addressable non-volatile memory (NVM) is promising for the next-generation memory system. However, NVM suffers from limited write endurance, as an NVM cell will wear out very soon after a certain number of writes, making NVM undependable. To address this issue, many wear reduction and leveling mechanisms have been proposed. Nevertheless, most of these mechanisms are developed without the knowledge of application semantics and behaviors. In this paper, we advocate application-level wear management, which allows us to create effective and flexible wear reduction and leveling techniques for specific application domains. Particularly, we find that applications running with dynamic binary translation (DBT) exhibit significantly more writes. This is because DBT systems need to handle architectural differences when translating instructions across different architectures. In this paper, we present WDBT, which focuses on wear reduction and leveling for DBT systems on NVM. WDBT is designed based on common practices of DBT systems to reduce the majority of writes introduced by DBT. We also implement a prototype of WDBT using a real-world DBT system, QEMU, for multiple popular instruction sets. Experimental results on SPEC CPU 2017 show that WDBT can effectively reduce writes by 52.09% and 34.48% for x86-64 and RISC-V, respectively. Moreover, the performance overhead of WDBT is negligible.
Year
DOI
Venue
2022
10.1016/j.jss.2022.111247
Journal of Systems and Software
Keywords
DocType
Volume
Non-volatile memory,NVM Wear leveling,NVM Wear reduction,Cross-ISA virtualization,Dynamic binary translation,QEMU
Journal
187
ISSN
Citations 
PageRank 
0164-1212
0
0.34
References 
Authors
0
6
Name
Order
Citations
PageRank
Jin Wu121.37
Jian Dong211.38
Ruili Fang311.02
Wen Zhang400.68
Wenwen Wang500.68
Decheng Zuo600.34