Name
Title | ||
|---|---|---|
An FPGA-Based High-Frequency Trading System for 10 Gigabit Ethernet with a Latency of 433 ns |
Abstract | ||
|---|---|---|
High-frequency trading (HFT) systems require extremely low latency in response to market feeds to make profits. In order to reduce latency, the system is implemented with a 10 gigabit Ethernet physical transceiver with a low latency of 25 ns, custom network stack parsing and packaging, partial financial protocol decoding and encoding, order book handling and custom trading strategy. The hardware t... |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/VLSI-DAT54769.2022.9768065 | 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | DocType | ISBN |
Protocols,Ethernet,TCPIP,Life estimation,Very large scale integration,Packaging,Hardware | Conference | 978-1-6654-0921-6 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-Chieh Kao | 1 | 0 | 0.34 |
| Hung-An Chen | 2 | 0 | 0.34 |
| Hsi-Pin Ma | 3 | 0 | 0.34 |